1. Field of the Invention
The present invention relates to an amplifier and an analog/digital converter using the amplifier.
2. Description of Related Art
An analog/digital converter (A/D converter) includes a comparator that compares an analog voltage signal with reference voltage. This comparator has an input-referred offset, and this offset varies depending on the manufacturing process. Thus, as shown in FIG. 5 in the specification of U.S. Pat. No. 4,602,167, for example, the signal input to the comparator is amplified by a preamp to the signal level that is sufficiently larger than the input-referred offset. A preamp that is disclosed in the specification of U.S. Pat. No. 4,602,167 is a typical differential amplifier that includes a constant current source between an input transistor pair and a power supply. As such a preamp is included, signal comparison can be performed with high accuracy. However, the current needs to be constantly flowed, which increases power consumption.
Meanwhile, FIG. 17 shows a circuit diagram of a sense amplifier shown in FIG. 2 of an article by Schinkel et al., titled “A Double-Tail Latch-Type Voltage Sense Amplifier with 18 ps Setup+Hold Time” (Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, February 2007, pp. 314-315, 605). This sense amplifier includes input transistors N1, N2 that are NMOS transistors, load transistors P1, P2 that are PMOS transistors, and a switch transistor N3 that is an NMOS transistor. Here, input signals VinP and VinN are input to gates of the input transistors N1, N2, respectively. Further, a clock signal CLK is input to gates of the load transistors P1, P2 and a gate of the switch transistor N3. Thus, the load transistors P1, P2 and the switch transistor N3 are turned on or off in a complementary manner.
More specifically, when the clock signal CLK is H (High), the load transistors P1, P2 are OFF, and the switch transistor N3 is ON, which means an amplification period. On the other hand, when the clock signal CLK is L (Low), the load transistors P1, P2 are ON, the switch transistor N3 is OFF, which means a reset period. In the reset period, both of output signals VoutP, VoutN are reset to a power supply voltage VDD. In the reset period, the switch transistor N3 is OFF, and the current is interrupted. Thus, the power consumption is decreased than in the preamp in the specification of U.S. Pat. No. 4,602,167. The similar sense amplifier is disclosed also in FIG. 1 of Japanese Unexamined Patent Application Publication No. 11-176163. Further, a technique of adjusting an offset amount using a variable capacitor is disclosed in the specification of U.S. Pat. No. 6,728,240.